The present invention relates to semiconductor devices and methods of manufacturing semiconductor devices. The present invention has particular applicability to double-gate devices.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.
Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, two gates may be used to control short channel effects. A FinFET is a recent double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
Implementations consistent with the present invention provide a FinFET device with two gates that are formed on opposite sides of a conductive fin. The device may include gate material below the conductive fin to increase the total channel width for the device.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a semiconductor device that includes a substrate, an insulating layer, a first gate and a fin. The insulating layer is formed on the substrate and the first gate is formed on the insulating layer. The first gate has a U-shaped cross-section at a channel region of the semiconductor device. The fin has a number of side surfaces, a top surface and a bottom surface, where the bottom surface and at least a portion of the side surfaces are surrounded by the first gate.
According to another aspect of the invention, a method of manufacturing a semiconductor device is provided. The method includes forming an insulating layer on a substrate and forming a fin structure on the insulating layer. The fin structure has a number of side surfaces, a top surface and a bottom surface. The method also includes forming a dielectric layer over the top surface of the fin structure, forming source and drain regions and etching the insulating layer to laterally undercut the insulating layer below the bottom surface of the fin structure. The method further includes depositing a gate material over the fin structure, where the gate material surrounds the bottom surface of the fin structure and at least a portion of the side surfaces. The method also includes planarizing the deposited gate material, patterning and etching the gate material to form a first and a second gate electrode on opposite sides of the fin.
According to a further aspect of the invention, a semiconductor device that includes a substrate, an insulating layer, a conductive fin, a dielectric cap, a gate dielectric layer and a gate is provided. The insulating layer is formed on the substrate and the conductive fin is formed on the insulating layer. The conductive fin has a first end, a second end and a middle portion located between the first and second ends, where the first and second ends are disposed on the insulating layer and the middle portion is separated from the insulating layer. The dielectric cap is formed over a top surface of the conductive fin and a gate dielectric layer is formed on side surfaces and a bottom surface of the conductive fin. The gate is formed on the insulating layer and the gate surrounds the bottom surface and side surfaces of the middle portion of the conductive fin.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.